The present invention generally relates to semiconductor devices and more particularly to a process for fabricating an integrated circuit having an increased integration density.
In the fabrication of large-scale integrated circuits such as the dynamic random access memory (DRAM) devices, an enormous number of semiconductor devices are formed on a common semiconductor substrate or wafer. Generally, the fabrication process of such a memory device includes an optical exposure process of the wafer, wherein a pattern of the semiconductor device to be formed is projected on the wafer by an optical system. Thereby, it is well known that the integration density of the device is limited by the resolution of the optical system used for the exposure process.
It is well known that the resolution limit R is related to the wavelength .lambda. of the light used for the exposure and the numerical aperture N.sub.A of the optical system according to the relationship EQU R.infin..lambda./N.sub.A. (1)
This equation indicates that the resolution limit of the exposure is improved when a light having a shorter wavelength is used for the exposure. Further, this equation indicates that the resolution is improved by using an optical system having a larger numerical aperture. In other words, when there is a limitation in the reduction of the wavelength of the light that is available for the exposure, there is still a possibility of increasing the resolution of the exposure by employing an optical system having an increased numeric aperture.
On the other hand, it is known that there holds a relationship between the focal depth 1 of the optical system and the numerical aperture N.sub.A as EQU 1.infin..lambda./N.sub.A.sup.2. (2)
Thereby, it will be understood that the focal depth 1 inevitably decreases steeply with increasing numerical aperture N.sub.A and the proper focusing on the pattern on the wafer becomes difficult. This problem becomes particularly acute when exposing a large area of the wafer by a single exposure process. More specifically, when a large area is exposed by an optical beam, the focusing at the marginal part of the area inevitably becomes poor even when a proper focusing is established at the central part of the area. This effect is known as the astigmatic difference. Further, the surface of the wafer is not entirely flat but generally forms a gentle undulation. When such an undulation exists, the focusing by the optical system of large numerical aperture becomes extremely difficult.
In order to overcome the problem of small focal length associated with the use of large numerical aperture optical system, various designs of semiconductor devices are proposed.
FIG. 1 shows a schematical relationship between the pattern size and the focal depth in an optical system of a given numerical aperture. As can be seen in FIG. 1, the focal depth 1 decreases with decreasing pattern size and reaches a zero-focal depth at a pattern size S. This size S corresponds to the resolution limit. On the other hand, when the pattern size is increased, the focal depth 1 increases. This means that a pattern can be exposed on the wafer with substantial tolerance in the focusing when the size of the pattern is relatively large, while a pattern having a relatively small size has to be focused exactly and without tolerance. When the proper focusing is failed, the image of the pattern transferred on the wafer may be blurred. Alternatively, one may not obtain sufficient optical energy to cause the desired exposure. The above relationship indicates that the patterning of small contact holes is particularly difficult.
In order to avoid the problem of reduced focal depth in the patterning of minute semiconductor patterns, various designs of semiconductor device have been proposed so far.
FIG. 2(A) shows a typical example of a DRAM in the plan view, wherein a number of bit lines BL and word lines WL are arranged in the row and column directions to form a criss-cross pattern. As usual in the DRAM device, a thin silicon oxide film is provided to cover the surface of the semiconductor wafer and there is formed an elongated device region 73 such that the surface of the wafer is exposed at the device region 73.
It should be noted that the device region 73 is formed to extend in a direction oblique to the bit lines BL and hence to the word lines WL. By forming the device region 73 as such, one can form a contact hole 75 for a stacked capacitor Q to be described later in a part located between a pair of adjacent bit lines BL. Thereby, one can increase the separation between adjacent two bit lines and hence the width of each bit line.
On the other hand, a contact hole 78 for the bit line BL is formed in the device region 73 in correspondence to where the device region 73 crosses the bit line BL. Thereby, the contact hole 78 is formed between a pair of adjacent word lines WL. and the word lines WL are separated from each other by the contact hole 78. Particularly, the size of the bit line BL is increased in correspondence to a part where the contact hold 78 is formed. Further, the word line WL is bent to avoid the contact hold 78 on the bit line BL as illustrated.
FIG. 2(B) shows the cross sectional view of the DRAM of FIG. 2(A), wherein the memory device is formed on a p-type silicon substrate 71 covered by a field oxide film 72, and the field oxide film 72 is formed with the device region 73 that extends obliquely to the word lines WL and bit lines BL in the plan view as already described.
On the exposed surface of the device region 73, an n.sup.+ -type diffusion region 74 and another n.sup.+ -type diffusion region 77 are formed, with a p-type channel region CH formed therebetween, and the word line WL is formed to extend over the channel region CH when crossing the device region 73. Thereby, the word line WL forms a gate electrode of a MOS transistor. As is well known, there is a thin gate insulation film formed immediately under the word line WL. In the illustrated cross section, there is another word line WL extending on the filed oxide film 72. Further, an insulating layer 70 is deposited on the field oxide film 72 to bury the word lines WL as well as to cover the device region 73, and the contact hole 78 shown in the plan view of FIG. 2(A) is formed to expose the n.sup.+ -type diffusion region 77 via the contact hole 78. Simultaneously, the contact hole 75 shown in the plan view of FIG. 2(A) is formed to expose the n.sup.+ -type diffusion region 74 acting as a source of MOSFET, and the stacked capacitor Q having a number of capacitor fins 76 is formed in contact with the diffusion region 74 via the contact hole 75. Further, the bit line BL is formed in contact with the diffusion region 77 that acts as the drain of MOSFET. Further, the entire structure is covered by an protective film.
As already noted, the device of FIG. 2(A) is designed to allow the use of bit lines and word lines that have a substantial Pattern width and pitch, and one can minimize the problem of focal depth as long as the patterning of the word lines and the bit lines are concerned. On the other hand, the patterning of the contact holes still involves a significant difficulty due to the reduced size of the contact hole.